Map out the physical channels to your DUT pins.
The TDC is the central hub for all V93000 documentation. It is a searchable, interactive help system that integrates directly with SmarTest (accessible via ) and as a standalone application. verigy 93k tester manual
Using C++ and specialized test methods. Debugging: Utilizing the debugger to analyze failure data. Map out the physical channels to your DUT pins
A pattern file contains a sequential list of vectors. Every vector line represents one tester cycle. The format specifies the state of each pin using standard characters: 1 / 0 : Drive logic high / Drive logic low. H / L : Expect logic high / Expect logic low from the DUT. X : Ignore (don't care) the output of the DUT. Z : Put tester channel into high-impedance mode. Sequencer Instructions Using C++ and specialized test methods
A graphical and hierarchical representation of the execution sequence. It controls the exact path a device takes based on pass/fail criteria.
